Selecting Alternative Metals for Advanced Interconnects

• Main Authors: Soulié, Jean-Philippe, Sankaran, Kiroubanand, Van Troeye, Benoit, Leśniewska, Alicja, Pedreira, Olalla Varela, Oprins, Herman, Delie, Gilles, Fleischmann, Claudia, Boakes, Lizzie, Rolin, Cédric, Ragnarsson, Lars-Åke, Croes, Kristof, Park, Seongho, Swerts, Johan, Pourtois, Geoffrey, Tőkei, Zsolt, Adelmann, Christoph
• Format: Journal Article
• Language: English
• Published: 13-06-2024
• Subjects: Physics - Applied Physics; Physics - Materials Science
• DOI: 10.48550/arxiv.2406.09106

Interconnect resistance and reliability have emerged as critical factors
limiting the performance of advanced CMOS circuits. With the slowdown of
transistor scaling, interconnect scaling has become the primary driver of
continued circuit miniaturization. The associated scaling challenges for
interconnects are expected to further intensify in future CMOS technology
nodes. As interconnect dimensions approach the 10 nm scale, the limitations of
conventional Cu dual-damascene metallization are becoming increasingly
difficult to overcome, spurring over a decade of focused research into
alternative metallization schemes. The selection of alternative metals is a
highly complex process, requiring consideration of multiple criteria, including
resistivity at reduced dimensions, reliability, thermal performance, process
technology readiness, and sustainability. This tutorial introduces the
fundamental criteria for benchmarking and selecting alternative metals and
reviews the current state of the art in this field. It covers materials nearing
adoption in high-volume manufacturing, materials currently under active
research, and potential future directions for fundamental study. While early
alternatives to Cu metallization have recently been introduced in commercial
CMOS devices, the search for the optimal interconnect metal remains ongoing.