Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices
The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the...
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Main Authors: | , , , , , , |
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Format: | Journal Article |
Language: | English |
Published: |
12-09-2022
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Subjects: | |
Online Access: | Get full text |
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Summary: | The state-of-the-art CMOS technology has started to adopt three-dimensional
(3D) integration approaches, enabling continuous chip density increment and
performance improvement, while alleviating difficulties encountered in
traditional planar scaling. This new device architecture, in addition to the
efforts required for extracting the best material properties, imposes a
challenge of reducing the thermal budget of processes to be applied everywhere
in CMOS devices, so that conventional processes must be replaced without any
compromise to device performance. Ultra-violet laser annealing (UV-LA) is then
of prime importance to address such a requirement. First, the strongly limited
absorption of UV light into materials allows surface-localized heat source
generation. Second, the process timescale typically ranging from nanoseconds
(ns) to microseconds ({\mu}s) efficiently restricts the heat diffusion in the
vertical direction. In a given 3D stack, these specific features allow the
actual process temperature to be elevated in the top-tier layer without
introducing any drawback in the bottom-tier one. In addition, short-timescale
UV-LA may have some advantages in materials engineering, enabling the
nonequilibrium control of certain phenomenon such as crystallization, dopant
activation, and diffusion. This paper reviews recent progress reported about
the application of short-timescale UV-LA to different stages of CMOS
integration, highlighting its potential of being a key enabler for next
generation 3D-integrated CMOS devices. |
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DOI: | 10.48550/arxiv.2209.05337 |