High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

• Published in: Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004 pp. 854 - 859
• Main Authors: Van der Plas, G., Badaroglu, M., Vandersteen, G., Dobrovolny, P., Wambacq, P., Donnay, S., Gielen, G., De Man, H.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 07-06-2004; IEEE; Association for Computing Machinery
• Series: ACM Conferences
• Subjects: Applied sciences; Capacitance; Circuit noise; Circuit properties; Circuit simulation; Computational modeling; Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies; Coupling circuits; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Hardware > Hardware validation > Functional verification; Hardware > Hardware validation > Functional verification > Simulation and emulation; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit noise; Integrated circuits; Power supplies; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; model order reduction; substrate noise; modeling; Gating circuits; Computation time; Circuit design; Interconnection; Complementary MOS technology; Integrated circuit; Digital circuit; SPICE; Circuit noise; Computer aided design
• ISBN: 1581138288; 9781581138283; 1511838288
• ISSN: 0738-100X
• DOI: 10.1145/996566.996794

Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..