An efficient method for multi-level approximate logic synthesis under error rate constraint

• Published in: 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
• Main Authors: Yi Wu, Weikang Qian
• Format: Conference Proceeding
• Language: English
• Published: IEEE 05-06-2016
• Subjects: Approximate computing; Approximation algorithms; Boolean functions; Error analysis; Hardware; Heuristic algorithms; Inexact circuit; Logic synthesis; Signal processing algorithms
• DOI: 10.1145/2897937.2897982

Approximate computing is an emerging design paradigm targeting at error-tolerant applications. It trades off accuracy for improvement in hardware cost and energy efficiency. In this paper, we propose a novel approach for multi-level approximate logic synthesis under error rate constraint. The basic idea of our approach is to pick nodes in a Boolean network and shrink them by approximating their factored-form expressions. We propose two different algorithms to implement the basic idea. The first algorithm iteratively picks the most effective node at present to shrink. Its drawback lies in that it may need a large number of iterations. To overcome this drawback, the second algorithm formulates a knapsack problem to pick multiple nodes for shrinking simultaneously. It is still iterative, but the number of iterations is greatly reduced. We apply the two algorithms to MCNC benchmarks and arithmetic circuits including adders and multipliers. The experimental results demonstrated that our algorithms perform better in area saving and are 1.7 and 5.9 times faster, respectively, compared with the state-of-the-art approach.