Synthesis of statically analyzable accelerator networks from sequential programs

• Published in: 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp. 1 - 8
• Main Authors: Shaoyi Cheng, Wawrzynek, John
• Format: Conference Proceeding
• Language: English
• Published: ACM 01-11-2016
• Subjects: Computational modeling; Field programmable gate arrays; Hardware; hardware accelerator; High level synthesis; Kernel; Peer-to-peer computing; process network; system design flow; System recovery
• ISSN: 1558-2434
• DOI: 10.1145/2966986.2967077

This paper describes a general framework for transforming a sequential program into a network of processes, which are then converted to hardware accelerators through high level synthesis. Also proposed is a complementing technique for performing static deadlock analysis of the generated accelerator network. The interactions between the accelerators' schedules, the capacity of the communication channels in the network and the memory access mechanisms are all incorporated into our model, such that potential artificial deadlocks can be detected and resolved a priori. An algorithm optimized for FPGA implementation is developed and applied through our transformation framework. A set of irregular computation kernels are converted into networks of FPGA accelerators. Compared to hardware accelerators generated without our transformation, the accelerator networks achieve significantly better performance.