Regaining throughput using completion detection for error-resilient, near-threshold logic

• Published in: DAC Design Automation Conference 2012 pp. 974 - 979
• Main Authors: Crop, Joseph, Pawlowski, Robert, Chiang, Patrick
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 03-06-2012; IEEE
• Series: ACM Conferences
• Subjects: Adders; Clocks; Completion Detection; Delay; Error Detection; Hardware > Very large scale integration design; Logic gates; Low Power; Noise; Throughput; Variation Tolerance; low power; completion detection; error detection; variation tolerance
• ISBN: 1450311997; 9781450311991
• ISSN: 0738-100X
• DOI: 10.1145/2228360.2228535

Operating in the near-threshold regime can result in significant energy savings. Unfortunately, the increased timing variation prevents conventional error-detection techniques from properly functioning. This paper introduces two circuit-level timing error detection techniques that aim to increase throughput while operating in the near-threshold voltage regime: current-sensing completion detection and transition-aware completion detection. Each method allows any digital circuit to operate at speeds not limited by the worst-case critical path. Throughput improvements and energy savings are reported for implementations on a 16-bit adder.