NoC-sprinting: Interconnect for fine-grained sprinting in the dark silicon era

• Published in: 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) pp. 1 - 6
• Main Authors: Jia Zhan, Yuan Xie, Guangyu Sun
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2014
• Subjects: Computational Sprinting; Dark Silicon; Multicore processing; Network topology; Network-on-Chip; Routing; Silicon; Switches; System recovery; Topology
• ISSN: 0738-100X
• DOI: 10.1145/2593069.2593165

The rise of utilization wall limits the number of transistors that can be powered on in a single chip and results in a large region of dark silicon. While such phenomenon has led to disruptive innovation in computation, little work has been done for the Network-on-Chip (NoC) design. NoC not only directly influences the overall multi-core performance, but also consumes a significant portion of the total chip power. In this paper, we first reveal challenges and opportunities of designing power-efficient NoC in the dark silicon era. Then we propose NoC-Sprinting: based on the workload characteristics, it explores fine-grained sprinting that allows a chip to flexibly activate dark cores for instantaneous throughput improvement. In addition, it investigates topological/routing support and thermal-aware floorplanning for the sprinting process. Moreover, it builds an efficient network power-management scheme that can mitigate the dark silicon problems. Experiments on performance, power, and thermal analysis show that NoC-sprinting can provide tremendous speedup, increase sprinting duration, and meanwhile reduce the chip power significantly.