LATA: A latency and Throughput-Aware packet processing system

• Published in: Design Automation Conference pp. 36 - 41
• Main Authors: Jilong Kuang, Bhuyan, Laxmi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2010
• Subjects: Algorithm design and analysis; Computer science; Delay; multicore architecture; Multicore processing; packet processing; Parallel processing; Parallel-pipelining; Pipeline processing; Protocols; Scheduling algorithm; Throughput; Uniform resource locators
• ISBN: 9781424466771; 1424466776
• ISSN: 0738-100X
• DOI: 10.1145/1837274.1837286

Current packet processing systems only aim at producing high throughput without considering packet latency reduction. For many real-time embedded network applications, it is essential that the processing time not exceed a given threshold. In this paper, we propose LATA, a LAtency and Throughput-Aware packet processing system for multicore architectures. Based on parallel pipeline core topology, LATA can satisfy the latency constraint and produce high throughput by exploiting fine-grained task-level parallelism. We implement LATA on an Intel machine with two Quad-Core Xeon E5335 processors and compare it with four other systems (Parallel, Greedy, Random and Bipar) for six network applications. LATA exhibits an average of 36.5% reduction of latency and a maximum of 62.2% reduction of latency for URL over Random with comparable throughput performance.