Simulation bridge a framework for multi-processor simulation

• Published in: International Conference on Hardware Software Codesign: Proceedings of the tenth international symposium on Hardware/software codesign; 06-08 May 2002 pp. 49 - 54
• Main Authors: Nagendra, G. D., Kumar, V. G. Prem, Chakravarthy, B. S. Sheshadri
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 06-05-2002; IEEE
• Series: ACM Conferences
• Subjects: Bridges; Computational modeling; Computer architecture; Computer peripherals; Computer systems organization > Embedded and cyber-physical systems; Computer systems organization > Real-time systems; Computing methodologies > Modeling and simulation; Computing methodologies > Modeling and simulation > Simulation evaluation; Context modeling; Controllability; Digital signal processors; Embedded computing; General and reference > Cross-computing tools and techniques > Performance; Hardware > Communication hardware, interfaces and storage; High performance computing; Observability; Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Process management > Multiprocessing > multiprogramming > multitasking; Software and its engineering > Software organization and properties > Software system structures > Software architectures > Simulator > interpreter; multiprocessor simulation; instruction set simulator; simulation framework
• ISBN: 1581135424; 9781581135428
• DOI: 10.1145/774789.774800

Multi-processor solutions in the embedded world are being designed to meet the ever increasing computational demands of the emerging applications. Such architectures comprise two or more processors (often a mix of general purpose and digital signal processors) together with a rich peripheral mix to provide a high performance computational platform. While there are many simulation solutions in the industry available to address the system partitionaing issues and also the verification of HW-SW interactions in these complex systems, there are very few solutions targetted towards the SW application developers' needs.The primary concern of the SW application developers is to debug and optimize their code. Hence, cycle accuracy and performance of the simulation solution becomes the key enablers. Desired observability and controllability of the models are additional careabouts. Secondly, application devlopers are more comfortable at instruction level simulations than they are with RTL or gate level simulation. These specific requirements have a bearing on the choices in the simulation solutions.This paper describes the design of a generic, C based multi-processor instruction set simulator framework in the context of the above parameters. This framework, termed the "simulation bridge", facilitates highly accurate, yet efficient simulation. The SimBridge performs clock correct lock-step simulation of the models in the architecture using a global simulation engine that handles both intra-processor and inter-processor communication in a homogenous fashion. It addresses the multiple key issues of execution control, synchronization, connectivity and communication.The paper concludes with the performance analysis of the SimBridge in an experimental test setup as well as in the Texas Instruments (TI) TMS320C54x-based simulators.