Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches

• Published in: 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture pp. 351 - 362
• Main Authors: Miller, T N, Thomas, R, Dinan, J, Adcock, B, Teodorescu, R
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2010
• Subjects: Decoding; Error analysis; Error correction; Error correction codes; Hardware; Random access memory; Transistors
• ISBN: 1424490715; 9781424490714
• ISSN: 1072-4451
• DOI: 10.1109/MICRO.2010.28

Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very close to the transitor's threshold voltage, into what is called the near-thresold region. This reduces power consumption dramatically but also decreases reliability by orders of magnitude, especially for SRAM structures such as caches. This paper presents Parichute, a novel and powerful error correction technique based on turbo product codes that allows caches to continue to operate in near-threshold, while trading off some cache capacity to store error correction information. Our Parichute-based cache implementation is flexible, allowing protection to be disabled in error-free high voltage operation and selectively enabled as the voltage is lowered and the error rate increases. Parichute is also self-testing and variation-aware, allowing selective protection of cache sections that exhibit errors at higher supply voltages because of process variation. Parichute achieves significantly stronger error correction compared to prior cache protection techniques, enabling 2× to 4× higher cache capacity at low voltages. Our results also show that a system with a Parichute-protected L2 cache can achieve a 34% reduction in system energy (processor and DRAM) compared to a system operating at nominal voltage.