A functional-level test generation methodology using two-level representations

• Published in: 26th ACM/IEEE Design Automation Conference pp. 722 - 725
• Main Authors: Davé, U. J., Patel, J. H.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01-06-1989
• Series: ACM Conferences
• Subjects: Boolean functions; Circuit faults; Circuit testing; Combinational circuits; Data structures; Digital circuits; Hardware > Hardware test > Test-pattern generation and fault simulation; Hardware > Integrated circuits > Logic circuits > Combinational circuits; Logic testing; Materials testing; Permission; System testing
• ISBN: 0897913108; 9780897913102
• ISSN: 0738-100X
• DOI: 10.1145/74382.74513

This paper proposes the use of a functional-level testing methodology based on the generation of test vectors from the functional descriptions of combinational circuits under test. The approach that is adopted involves the generation of a two-level AND-OR, or OR-AND implementation from a circuit's functional description, the generation of test vectors by way of a PODEM based algorithm for the two-level implementation, and the application of the generated tests on a specific implementation(s) of the circuit under test. This approach is experimentally evaluated on various combinational circuits, and is shown to be successful in achieving very high fault-coverages without relying on implementation details of the circuits that are tested.