Demonstration of Metal-Gated Low V@@dt@ n-MOSFETs Using a Poly-Si/TaN/Dy@@d2@O@@d3@/SiON Gate Stack With a Scaled EOT Value

• Published in: IEEE electron device letters Vol. 28; no. 7; pp. 656 - 658
• Main Authors: Yu, H Y, Singanamalla, R, Ragnarsson, L.-A., Chang, V S, Cho, H.-J., Mitsuhashi, R, Adelmann, C, van Elshocht, S., Lehnen, P, Chang, S Z, Yin, K M, Schram, T, Kubicek, S, de Gendt, S., Absil, P, de Meyer, K, Biesemans, S
• Format: Journal Article
• Language: English
• Published: 01-07-2007
• ISSN: 0741-3106
• DOI: 10.1109/LED.2007.900308

In this letter, we report that by using a thin dysprosium oxide (Dy@@d2@O@@d3@)cap layer (approx. 1-nm thick) on top of SiON host dielectrics, the threshold voltage (V@@dt@) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy@@d2@O@@d3@ cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.