FLUX chip: design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75-mum LTS technology

• Published in: IEEE transactions on applied superconductivity Vol. 11; no. 1; pp. 326 - 332
• Main Authors: Dorojevets, M, Bunyk, P, Zinoviev, D
• Format: Journal Article
• Language: English
• Published: 01-03-2001
• ISSN: 1051-8223
• DOI: 10.1109/77.919349

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of ~25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of ~90,000 Josephson junctions on a ~10 mmx15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm(2), 1.75-mum Nb-trilayer technology