Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS : International Conference on Microelectronic Test Structures

Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS : International Conference on Microelectronic Test Structures

Saved in:
Bibliographic Details
Published in:IEEE transactions on semiconductor manufacturing Vol. 25; no. 2; pp. 155 - 161
Main Authors: CHEN, David C, LEE, Ryan, LIU, Yuan-Chang, LIN, Guan-Shyan, TANG, Mao-Chyuan, WANG, Meng-Fan, YEH, Chune-Sin, CHIEN, Shan-Chieh
Format: Journal Article
Language:English
Published: New York, NY Institute of Electrical and Electronics Engineers 2012
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Ultrathin films
Gate current
Oxide layer
Depletion layer
Tunnel effect
High precision
RF-CV
Radiofrequency
Modeling
history effect
silicon-on-insulator (SOI)
Thickness
Silicon on insulator technology
Gate capacitance
Parasitic component
Complementary MOS technology
gate leakage
Capacitance
Leakage current
Miniaturization
Floating body
T shape
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
ISSN:0894-6507
1558-2345