6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET

• Published in: 2017 IEEE International Solid-State Circuits Conference (ISSCC) pp. 114 - 115
• Main Authors: Im, Jay, Freitas, Dave, Roldan, Arianne, Casey, Ronan, Chen, Stanley, Chou, Adam, Cronin, Tim, Geary, Kevin, McLeod, Scott, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Upadhyaya, Parag, Zhang, Geoff, Frans, Yohan, Ken Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2017
• Subjects: Clocks; CMOS technology; Decision feedback equalizers; FinFETs; Receivers; System-on-chip; Timing
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2017.7870287

The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S 21 of a channel resembling such interconnects and the corresponding single-pulse response after TX-FIR and RX CTLE. Although the S 21 is merely ~10dB at 14GHz, the single-pulse response exhibits significant reflections from impedance discontinuities, mainly between package and PCB traces. These reflections are detrimental to PAM-4 signaling and cannot be equalized effectively by RX CTLE and/or a few taps of TX feed-forward equalization. This paper presents the design of a PAM-4 receiver using 10-tap direct decision-feedback equalization (DFE) targeting such VSR channels.