Toward Extreme-Scale Processor Chips

Toward Extreme-Scale Processor Chips

As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of die stacking. Transistors may not be much faster, but there will be many more of them. In these architectures, efficient communication and sy...

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Bibliographic Details
Published in:2016 IEEE 23rd International Conference on High Performance Computing (HiPC) p. 290
Main Author: Torrellas, Josep
Format: Conference Proceeding
Language:English
Published: IEEE 01-12-2016
Subjects:
Computer architecture
Computer science
Conferences
Hardware
Parallel processing
Synchronization
Transistors
Online Access:Get full text
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Summary:As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of die stacking. Transistors may not be much faster, but there will be many more of them. In these architectures, efficient communication and synchronization will be a challenge. Moreover, energy and power will constrain the designs even more than they do today. In this context, this talk presents some of the technologies that we may need to deploy to exploit these architectures. To enable data sharing, we need novelsynchronization and fence hardware. For low-latency communication, we may leverage on-chip wireless networks.
DOI:10.1109/HiPC.2016.041