3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET

• Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 68 - 70
• Main Authors: Frans, Yohan, McLeod, Scott, Hedayati, Hiva, Elzeftawi, Mohamed, Jin Namkoong, Lin, Winson, Im, Jay, Upadhyaya, Parag, Ken Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-01-2016
• Subjects: Clocks; CMOS integrated circuits; FinFETs; Logic gates; Multiplexing; Transceivers; Transmitters
• ISBN: 1467394661; 9781467394666
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2016.7417910

Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double from 32Gb/s to 64Gb/s while keeping the same power envelope. This paper presents the design of a 64Gb/s NRZ transmitter for short-reach electrical links in a 16nm FinFET process. It is applicable to standards such as CEI-56-VSR/MR, using power efficient techniques that take into considerations FinFET device properties: low DIBL, negligible body effect, low junction capacitance, low channel leakage, high intrinsic gain, high gate capacitance and resistance, high flicker noise, and steep CV curve in accumulation region.