3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE
In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) te...
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Published in: | 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) pp. 60 - 61 |
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01-02-2014
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Abstract | In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further improve the power efficiency over ET by replacing the linear PA with a switching PA driven by a phase signal [7]. However, to meet the specified low distortion, especially for LTE with a wide bandwidth baseband signal, an EER PA generally has difficulty achieving a wide bandwidth for the phase signal path, and requires a high-speed supply modulator, and highly accurate timing between envelope and phase signals. To overcome these problems, this paper introduces an envelope / phase generator based on a mixer and a timing aligner based on a delay-locked loop. Additionally, they were integrated with a switching PA and a supply modulator on the same die. |
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AbstractList | In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and high-power-efficiency CMOS power amplifier (PA). To improve the power efficiency of the conventional linear PA [1-4], an envelope tracking (ET) technique, which modulates supply voltage of a linear PA, has attracted attention. However, the published power efficiency, gain and output power are not sufficient for LTE applications [5], and its typical implementation requires an external supply modulator that is a high-speed power supply circuit [6]. Envelope elimination and restoration (EER) is an alternative supply modulation technique that can further improve the power efficiency over ET by replacing the linear PA with a switching PA driven by a phase signal [7]. However, to meet the specified low distortion, especially for LTE with a wide bandwidth baseband signal, an EER PA generally has difficulty achieving a wide bandwidth for the phase signal path, and requires a high-speed supply modulator, and highly accurate timing between envelope and phase signals. To overcome these problems, this paper introduces an envelope / phase generator based on a mixer and a timing aligner based on a delay-locked loop. Additionally, they were integrated with a switching PA and a supply modulator on the same die. |
Author | Shirai, Noriaki Murakami, Tomotoshi Yamaura, Shinji Yoshida, Eiji Sakai, Yasufumi Yamazaki, Hiroshi Oishi, Kazuaki Takauchi, Hideki Kano, Hideki Kudo, Masahiro Suto, Kazuo Kawano, Yoichi Tamura, Tetsuro Mori, Toshihiko Kawai, Shigeaki |
Author_xml | – sequence: 1 givenname: Kazuaki surname: Oishi fullname: Oishi, Kazuaki organization: Fujitsu Labs., Kawasaki, Japan – sequence: 2 givenname: Eiji surname: Yoshida fullname: Yoshida, Eiji organization: Fujitsu Labs., Kawasaki, Japan – sequence: 3 givenname: Yasufumi surname: Sakai fullname: Sakai, Yasufumi organization: Fujitsu Labs., Kawasaki, Japan – sequence: 4 givenname: Hideki surname: Takauchi fullname: Takauchi, Hideki organization: Fujitsu Labs., Kawasaki, Japan – sequence: 5 givenname: Yoichi surname: Kawano fullname: Kawano, Yoichi organization: Fujitsu Labs., Kawasaki, Japan – sequence: 6 givenname: Noriaki surname: Shirai fullname: Shirai, Noriaki organization: Fujitsu Semicond., Yokohama, Japan – sequence: 7 givenname: Hideki surname: Kano fullname: Kano, Hideki organization: Fujitsu Semicond., Yokohama, Japan – sequence: 8 givenname: Masahiro surname: Kudo fullname: Kudo, Masahiro organization: Fujitsu Semicond., Yokohama, Japan – sequence: 9 givenname: Tomotoshi surname: Murakami fullname: Murakami, Tomotoshi organization: Fujitsu Semicond., Yokohama, Japan – sequence: 10 givenname: Tetsuro surname: Tamura fullname: Tamura, Tetsuro organization: Fujitsu Semicond., Yokohama, Japan – sequence: 11 givenname: Shigeaki surname: Kawai fullname: Kawai, Shigeaki organization: Fujitsu Semicond., Yokohama, Japan – sequence: 12 givenname: Shinji surname: Yamaura fullname: Yamaura, Shinji organization: Fujitsu Semicond., Yokohama, Japan – sequence: 13 givenname: Kazuo surname: Suto fullname: Suto, Kazuo organization: Fujitsu Semicond., Yokohama, Japan – sequence: 14 givenname: Hiroshi surname: Yamazaki fullname: Yamazaki, Hiroshi organization: Fujitsu Labs., Kawasaki, Japan – sequence: 15 givenname: Toshihiko surname: Mori fullname: Mori, Toshihiko organization: Fujitsu Labs., Kawasaki, Japan |
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PublicationTitle | 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) |
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Snippet | In recent years, the demand for low cost and system-on-a-chip for mobile terminals has led to the development of a highly-integrated, low-distortion, and... |
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SubjectTerms | Bandwidth CMOS integrated circuits Delays Multiaccess communication Power amplifiers Spread spectrum communication |
Title | 3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE |
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