A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 278 - 279
• Main Authors: McLachlan, R. C., Gillespie, A., Coln, M. C. W., Chisholm, D., Lee, D. T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2013
• Subjects: Calibration; Force; Immune system; Noise; Resistance; Resistors; Switches
• DOI: 10.1109/ISSCC.2013.6487734
• EISSN: 2376-8606
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530

DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DAC's code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature. However, this preferred architecture for noise and temperature drift suffers from several sources of INL including: resistor mismatch, voltage losses across CMOS switches, and the nonlinearity of each resistor.