Monolithic mixed-mode implementation of sum-of-product arrays for performing binary morphological image processing

Monolithic mixed-mode implementation of sum-of-product arrays for performing binary morphological image processing

This paper presents a monolithic mixed-mode implementation of sum-of-product arrays that are capable of performing morphological image processing in silicon. The digital equations of the two basic morphological operations, erosion and dilation, are rewritten in a local, mixed-mode form to facilitate...

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Bibliographic Details
Published in:1997 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 2; pp. 1421 - 1424 vol.2
Main Authors: Spencer, R.G., Sanchez-Sinencio, E.
Format: Conference Proceeding
Language:English
Published: IEEE 1997
Subjects:
Aggregates
Equations
Hardware
Image analysis
Image processing
Morphological operations
Morphology
Pixel
Silicon
Video coding
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Summary:This paper presents a monolithic mixed-mode implementation of sum-of-product arrays that are capable of performing morphological image processing in silicon. The digital equations of the two basic morphological operations, erosion and dilation, are rewritten in a local, mixed-mode form to facilitate hardware implementation and results are shown for a 3/spl times/3 selective element array fabricated in silicon.
ISBN:9780780335837
078033583X
DOI:10.1109/ISCAS.1997.622172