Low-frequency noise in high-k LaLuO3/TiN MOSFETs

• Published in: 2011 International Semiconductor Device Research Symposium (ISDRS) pp. 1 - 2
• Main Authors: Olyaei, M., Malm, B. G., Litta, E. D., Hellstrom, P-E, Ostling, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2011
• Subjects: High K dielectric materials; Logic gates; Low-frequency noise; MOSFETs; Semiconductor device modeling; Tin
• ISBN: 9781457717550; 1457717557
• DOI: 10.1109/ISDRS.2011.6135204

The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap densities appeared at the high-k interface or in the bulk, mobility degradation and enhancement in the level of low-frequency noise [1]. Previously low-frequency noise in devices with PtSi Schottky-barrier source/drain contacts were studied [2]. In this work the low-frequency noise characterization of MOSFETs with high-k LaLuO 3 dielectric and TiN gate is presented. The devices were fabricated on an SOI substrate thinned down to 30 nm by sacrificial dry oxidation and HF wet etching. Active areas were patterned through MESA etching. The process was continued with an optional growth of a 5 nm layer of thermal oxide on the wafers. The high-k LaLuO 3 dielectric was deposited by MBE (t LaLuO3 =6 nm) and the metal TiN gate by sputtering (t TiN =20 nm). This was followed by in-situ deposition of phosphorus doped poly-Si with t poly =150 nm. For the reference wafer, the high-k deposition was skipped. PtSi Schottky-barrier source/drain with Boron and Arsenic implantation was carried out for pMOSFETs and nMOSFETs respectively. In the next step, RTA at 700°C was performed for dopant segregation at the PtSi/Si interface. The fabrication process was finalized by metallization and FGA (10% H 2 in N 2 at 400° C for 30 min).