Session 19 overview / energy-efficient digital: Low-power digital techniques

• Published in: 2011 IEEE International Solid-State Circuits Conference pp. 330 - 331
• Main Authors: Kosonocky, Stephen, Chao, Ming-Yang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2011
• Subjects: CMOS technology; Energy efficiency; Energy harvesting; Integrated circuit reliability; Logic gates; Nonvolatile memory; Voltage
• ISBN: 1612843034; 9781612843032
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2011.5746452

Summary form only given. Next-generation low-power applications such as biological signal processing, energy scavenging and wireless communications require new technologies and circuit techniques to achieve the lowest energy-per-operation. These applications are driving new techniques for efficient on-die clock generation, level conversion, non-volatile storage, low-power clocking, and reliable low-voltage operation. Energy-efficient systems must be optimized to maximize the utility of power shut down during idle and low-activity periods while also maintaining low-energy operation and high throughput during active modes to meet performance targets. The papers selected for this session highlight technology enhancements, novel circuit techniques, and system designs targeting these goals.