Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design
This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger des...
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| Published in: | 2003 Electrical Overstress/Electrostatic Discharge Symposium pp. 1 - 9 |
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| Main Authors: | , , , , , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
01-09-2003
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| Abstract | This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um 2 . |
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| AbstractList | This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um 2 . |
| Author | Armer, J. Mohn, R. Keppens, B. Verhaege, K.G. Mergens, M.P.J. Taylor, G. Russ, C.C. De Ranter, F. Jozwiak, P.C. Cong Son Trinh |
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| Snippet | This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and... |
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| SubjectTerms | CMOS technology Costs Electronic ballasts Electrostatic discharge Europe Fingers MOS devices Protection Robustness Silicides |
| Title | Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design |
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