Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger des...

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Bibliographic Details
Published in:2003 Electrical Overstress/Electrostatic Discharge Symposium pp. 1 - 9
Main Authors: Keppens, B., Mergens, M.P.J., Armer, J., Jozwiak, P.C., Taylor, G., Mohn, R., Cong Son Trinh, Russ, C.C., Verhaege, K.G., De Ranter, F.
Format: Conference Proceeding
Language:English
Published: IEEE 01-09-2003
Subjects:
CMOS technology
Costs
Electronic ballasts
Electrostatic discharge
Europe
Fingers
MOS devices
Protection
Robustness
Silicides
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Summary:This paper describes a layout technique to optimize the ESD performance per area for fully silicided NMOS devices by segmenting the active area of drain and source regions. Efficient multi finger triggering is achieved by intrinsic inter-finger-coupling through the bulk enabled by compact finger design. The technique is successfully applied in a 0.13 um and a 0.18 um CMOS technology obtaining HBM ESD capability of up to 8.6 V/um 2 .