Numerical simulation of ultra-thin SOI transistor using non-isothermal energy balance model

• Published in: Proceedings. IEEE International SOI Conference pp. 33 - 34
• Main Authors: Apanovich, Y., Blakey, P., Cottle, R., Lyumkis, E., Polsky, B., Shur, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Accuracy; Electric variables; Impact ionization; Isothermal processes; Lattices; Numerical simulation; Predictive models; Semiconductor devices; Temperature; Thermal conductivity
• ISBN: 9780780324060; 0780324064
• DOI: 10.1109/SOI.1994.514221

Traditional semiconductor device simulators use the drift-diffusion and isothermal (constant lattice temperature) approximations. These can lead to poor accuracy in predicting the electrical characteristics of modern submicron devices, because non-local transport effects and self-heating effects are not taken into account. These effects are especially important for simulation of submicron SOI devices due to the low thermal conductivity of the underlying oxide layer. Non-local effects could lead to higher currents (velocity overshoot) and increased breakdown voltage compared with predictions of the drift-diffusion model, On the other hand self-heating effects lead to decreasing mobility and even negative output conductance for high gate biases, and decreased impact ionization rates for elevated lattice temperature. Therefore, a need for a device simulator that can account self-consistently non-local and self-heating effects for accurate simulation and optimization of SOI devices is important. The implementation of a self-consistent non-isothermal energy balance model in the general purpose device simulator ATLAS is described here. The simulation of an ultra-thin submicron SOI transistor is performed, and comparisons with simpler models are made. The impact of coupling the non-isothermal and non-local effects on device characteristics is shown.