Design, Fabrication and Characterization of High-Performance Silicon Nanowire Transistor

• Published in: 2008 8th IEEE Conference on Nanotechnology pp. 526 - 529
• Main Authors: Qiliang Li, Xiaoxiao Zhu, Yang Yang, Ioannou, D.E., Xiong, H.D., Suehle, J.S., Richter, C.A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2008
• Subjects: Annealing; Fabrication; FETs; Logic gates; Nanoscale devices; Performance evaluation; Silicon
• ISBN: 9781424421039; 1424421039
• ISSN: 1944-9399; 1944-9380
• DOI: 10.1109/NANO.2008.157

We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent current-voltage characteristics, low subthreshold slope ~85 mV/dec and high on/off current ratio ~10 6 . The Si nanowire devices are fabricated by using a self-aligned technique with standard photolithographic alignment and metal lift-off processes, enabling the large-scale integration of high-performance nanowire devices. We have also studied the effect of device structure and forming gas rapid thermal annealing on the nanowire transistor's electrical properties. We conclude that the self-aligned fabrication and non-overlapped gate-source/drain structure combined with appropriate post annealing leads to the excellent observed device performance.