Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

• Published in: Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 pp. 220 - 221
• Main Authors: Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Seungchul Lee, Jongho Yun, Wonsuk Cho, Hoon Lim, Jaikyun Park, Jaehun Jeong, Byoungkeun Son, Jaehoon Jang, Bonghyun Choi, Hoosung Cho, Kinam Kim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: CMOS technology; Costs; Lithography; MOS devices; MOSFETs; Oxidation; Plasma temperature; Random access memory; Semiconductor films; Thermal resistance
• ISBN: 4900784001; 9784900784000
• ISSN: 0743-1562
• DOI: 10.1109/.2005.1469275

In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the planar pull-down Tr., respectively in different levels, was developed and was reported in our previous study for low power applications. The previous reported S3 technology could not provide the high performance because it was developed for low power applications without salicide and high performance transistors. For the high performance transistor, the low thermal and low resistance processes are essential. In this study, the high performance CMOS transistors with 65nm gate length and l.6nm gate oxide, low resistance CVD Co for the small contact holes, and selectively formed CoSix in the peripheral area are added to the smallest 25F/sup 2/ double stacked S/sup 3/ SRAM cell for ultra high speed applications with the highest density such as 288M bits.