VLSI design and analysis of a critical-band processor for speech recognition

• Published in: IEEE International SOC Conference, 2004. Proceedings pp. 365 - 368
• Main Authors: Chao Wang, Yit-Chow Tong, Yu Shao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: CMOS technology; Computational complexity; Feature extraction; Frequency; Parallel processing; Pipelines; Speech analysis; Speech recognition; Very large scale integration; Voltage
• ISBN: 9780780384453; 0780384458
• DOI: 10.1109/SOCC.2004.1362466

The critical-band analysis plays a very important role in the frond-end feature extraction for speech recognition. In this paper, a generic low-power and low-voltage VLSI design of a critical-band transform (CBT) processor is proposed. Design and analysis of a 21-band Munich Bark scale CBT processor showed that it can achieve significant power-efficiency by the reduction in computational complexity, implementation of pipeline and parallel processing, and application of supply voltage scaling technique. Simulation results showed that it can complete a CBT analysis (including I/O process) in 4.99ms on one 160-point segment of speech at a very low system clock frequency of 234 kHz. This would support a CBT analysis for 50% overlap 10 ms segments of speech at a sampling frequency of 16 kHz. The power dissipation is 1413.6 /spl mu/W/MHz and 66.7 /spl mu/W/MHz for supply voltage of 3.3 V and 1.1 V, respectively. It contains 206273 transistors and occupies 2.69 mm/sup 2/ for a 0.35 /spl mu/m CMOS technology.