Development of a three-layer metal backend process for application to a submicron CMOS logic process

• Published in: Seventh International IEEE Conference on VLSI Multilevel Interconnection pp. 28 - 34
• Main Authors: Forester, L., Doedel, W., Osinski, K., Heesters, W.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1990
• Subjects: CMOS logic circuits; CMOS process; CMOS technology; Conductivity; Dielectrics; Etching; Manufacturing; Planarization; Resists; Very large scale integration
• DOI: 10.1109/VMIC.1990.127839

A three-layer metal process for application to a submicron logic process has been developed. The development was carried out in two phases. In phase 1, the metal-one and metal-two thicknesses were identical, and silicate sandwich planarization was used for both. This allowed the three-layer metal process to be run using existing technology in order to target device parameters and build up a reference for the phase 2 development. In phase 2, the metal-two thickness was adjusted to meet the resistivity used. The planarization allows for good critical dimension control of 1850-nm-thick metal three. Via string yields and resistivities have been shown to be sensitive to the siloxane type and processing conditions. With process modifications such as close-coupled bakes before metal deposition, the results with the siloxane have been comparable to those achieved with the reference silicate.< >