FPGA-Based Finite Impulse Response Filter Architecture Design with Distributed Arithmetic Logic to Reduce Power and Area

• Published in: Proceedings (IEEE Region 10 Symposium. Online) pp. 1 - 5
• Main Authors: Sattiraju, Suraj Siddharth, Odugu, Venkata Krishna
• Format: Conference Proceeding
• Language: English
• Published: IEEE 27-09-2024
• Subjects: Complexity theory; Computer architecture; Finite impulse response filters; FIR Filter; Hardware design languages; Logic; Low Power; LUT; OBC; Parallel processing; Software tools; Table lookup; Throughput; Topology
• ISSN: 2642-6102
• DOI: 10.1109/TENSYMP61132.2024.10751818

This work elucidates a DA Technique-based reconfigurable FIR Filter Architecture (FA) along with parallel processing reducing the complexity of the traditional multiplier while simultaneously increasing the throughput of the filter. The suggested FIR filter design utilizes block-processing which allows memory reuse in a systolic architecture. The LUT stores the filter coefficients and the required Partial Products (PP) are created using OBC-DA. The proposed OBC-based DA approach then performs multiplication in the main function block of the systolic architecture of the filter. Verilog HDL is used for coding, simulation, and synthesis using the Xilinx Vivado tool. The suggested filter architecture performance metrics are better in comparison with those of conventional filter architectures.