Python-LTSpice Framework for Impact Study of PCB Parasitics on Conducted Emission
This work presents a circuit pre-processing framework for LTSpice to identify main contributors to the common-mode conducted emission spectrum by iterative Python-controlled simulation, applying One-at-a-time sampling. For demonstration, a flyback DC/DC converter and the automotive CISPR25 measureme...
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Published in: | International Power Electronics and Motion Control Conference pp. 1 - 6 |
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Format: | Conference Proceeding |
Language: | English |
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IEEE
30-09-2024
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Abstract | This work presents a circuit pre-processing framework for LTSpice to identify main contributors to the common-mode conducted emission spectrum by iterative Python-controlled simulation, applying One-at-a-time sampling. For demonstration, a flyback DC/DC converter and the automotive CISPR25 measurement standard are used. The contribution of PCB parasitic capacitances to the CM emission spectrum is analyzed, as well as capacitive components of flyback transformer, SiC transistor switch and cable harness. The frequency range under consideration is CISPR band B and C from 150 kHz to 300 MHz. |
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AbstractList | This work presents a circuit pre-processing framework for LTSpice to identify main contributors to the common-mode conducted emission spectrum by iterative Python-controlled simulation, applying One-at-a-time sampling. For demonstration, a flyback DC/DC converter and the automotive CISPR25 measurement standard are used. The contribution of PCB parasitic capacitances to the CM emission spectrum is analyzed, as well as capacitive components of flyback transformer, SiC transistor switch and cable harness. The frequency range under consideration is CISPR band B and C from 150 kHz to 300 MHz. |
Author | Gsoels, Patrick D. Lopera, Jose Romero Stoiber, Martin Hackl, Herbert Auinger, Bernhard |
Author_xml | – sequence: 1 givenname: Jose Romero surname: Lopera fullname: Lopera, Jose Romero email: jose.lopera@silicon-austria.com organization: Silicon Austria Labs GmbH,Graz,Austria – sequence: 2 givenname: Patrick D. surname: Gsoels fullname: Gsoels, Patrick D. email: patrick.gsoels@silicon-austria.com organization: Silicon Austria Labs GmbH,Graz,Austria – sequence: 3 givenname: Herbert surname: Hackl fullname: Hackl, Herbert email: herbert.hackl@silicon-austria.com organization: Silicon Austria Labs GmbH,Graz,Austria – sequence: 4 givenname: Martin surname: Stoiber fullname: Stoiber, Martin email: martin.stoiber@silicon-austria.com organization: Silicon Austria Labs GmbH,Graz,Austria – sequence: 5 givenname: Bernhard surname: Auinger fullname: Auinger, Bernhard email: bernhard.auinger@silicon-austria.com organization: Silicon Austria Labs GmbH,Graz,Austria |
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Snippet | This work presents a circuit pre-processing framework for LTSpice to identify main contributors to the common-mode conducted emission spectrum by iterative... |
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SubjectTerms | circuit simulation common-mode conducted emission electromagnetic compatibility Iterative methods LTSpice Measurement standards Motion control Neural networks One-at-a-time sampling Optimization Power electronics Python sensitivity analysis Silicon carbide Switching circuits Training data Transistors |
Title | Python-LTSpice Framework for Impact Study of PCB Parasitics on Conducted Emission |
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