An Efficient Hardware Design and Implementation of Various Shift Register Types Using Chisel HDL

• Published in: 2024 11th International Conference on Electrical, Electronic and Computing Engineering (IcETRAN) pp. 1 - 5
• Main Authors: Petrovic, Marija L., Petkovic, Dejan D., Milovanovic, Vladimir M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 03-06-2024
• Subjects: Chisel hardware description language; CMOS technology; design generator; FPGA; Generators; Hardware; Hardware design languages; Logic gates; Random access memory; Shift registers; shift-register; SRAM macro
• DOI: 10.1109/IcETRAN62308.2024.10645179

This work demonstrates a hardware design generator of different types of shift registers suitable for both FPGA and ASIC technology mapping. A proposed hardware generator, written in Chisel HDL, supports a wide range of parameterization options, including input/output data type and bitwidth, shift-register depth, storage type (flip-flops, single-port, and dual-port SRAM), an optional AXI4-Stream, and a memory-mapped interface, among others. Various generator instances are tested and verified on a commercially available FPGA platform. An efficient and automated method for SRAM/BRAM macro replacement for FPGA and ASIC synthesis is presented. Synthesis results for TSMC 65 nm technology are given inside the paper.