A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera

• Published in: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
• Main Authors: Yang, Jiyue, Graening, Alexander, Romaszkan, Wojciech, Jacob, Vinod K., Gupta, Puneet, Pamarti, Sudhakar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-06-2024
• Subjects: Cameras; Compute-In-Memory Accelerator; Convolution; Deep learning; Energy efficiency; Event Camera; In-memory computing; Throughput; Very large scale integration
• ISSN: 2158-9682
• DOI: 10.1109/VLSITechnologyandCir46783.2024.10631484

We present a Compute-In-Memory (CIM) convolution accelerator for object tracking applications using event camera, which is a new imaging technology that significantly improves latency and dynamic range over conventional cameras. Previous works proposed an efficient ADC-Iess Stochastic CIM for deep learning but need to store 2^{\mathrm{N}} stochastic bits for an n-bit number. We propose to store binary numbers in memory and convert them to stochastic bits by in-situ Stochastic Number Generators on the fly, which reduce the storage requirement by >10x. The CIM macro embeds 32 tiny MAC units per weight and uses an early termination technique to skip unnecessary computation of zeros. The accelerator achieves energy efficiency of 485 TOPS/Wand throughput of 278-514 Mevent/s. The proposed SCIM macro can also be used to accelerate convolution in most deep learning applications.