Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction
Through the use of a lower impurity concentration in the gate poly-Si and lowering the post-annealing temperature, a highly reliable tunnel oxide process-technology has been developed. This process could become a key technology to realize high reliable Flash and NAND E super(2)PROM cells of 64Mb and...
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Published in: | Digest of technical papers - Symposium on VLSI Technology pp. 47 - 48 |
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Main Authors: | , , , , |
Format: | Journal Article |
Language: | English |
Published: |
01-01-1994
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Online Access: | Get full text |
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Summary: | Through the use of a lower impurity concentration in the gate poly-Si and lowering the post-annealing temperature, a highly reliable tunnel oxide process-technology has been developed. This process could become a key technology to realize high reliable Flash and NAND E super(2)PROM cells of 64Mb and beyond. |
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Bibliography: | SourceType-Scholarly Journals-2 ObjectType-Feature-2 ObjectType-Conference Paper-1 content type line 23 SourceType-Conference Papers & Proceedings-1 ObjectType-Article-3 |
ISSN: | 0743-1562 |