< e4 > E < /e4 > ffects of device design on InP-based HBT thermal resistance

• Published in: IEEE transactions on device and materials reliability Vol. 1; no. 4; pp. 185 - 189
• Main Authors: Thomas, S, Foschaar, J A, Fields, C H, Madhav, M M, Sokolich, M, Rajavel, R D, Shi, Binqiang
• Format: Magazine Article
• Language: English
• Published: 01-12-2001
• ISSN: 1530-4388
• DOI: 10.1109/7298.995832

The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 x 3 mum(2), the room temperature thermal resistance of the all-InP collector DHBT was 3.9 deg C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6 deg C/mW, while the SHBT had a thermal resistance of 12.3 deg C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f (T) from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz f(T) at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature