FPGA implementation of low power and high speed image edge detection algorithm

• Published in: Microprocessors and microsystems Vol. 75; p. 1
• Main Authors: Menaka, R, Janarthanan, R, Deeba, K
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier BV 01-06-2020
• Subjects: Algorithms; Data processing; Edge detection; Exploitation; Feature extraction; Feature recognition; Field programmable gate arrays; Hardware; Image processing; Object recognition; Pattern recognition; Pictures; Power management; Remote sensing
• DOI: 10.1016/j.micpro.2020.103053
• ISSN: 0141-9331

Image processing is a vital task in data processing system for applications in medical fields, remote sensing, microscopic imaging etc., Algorithms for processing image exist except for real time system style, hardware implementation is most popular principally. This paper presents a design for Sobel filter based edge detection on Field Programmable Gate Array (FPGA) board. Hardware implementation of the Sobel edge detection algorithm is chosen because it presents an honest scope for similarity over software package. On the opposite hand, Sobel edge detection will work with less deterioration in high level of noise. Edges are primarily the noticeable variation of intensities in a picture. Edges facilitate to spot the placement of an object and also the boundary of a selected entity within the image. It conjointly helps in feature extraction and pattern recognition. Hence, edge detection is of nice importance in pc vision. The planned design for edge detection exploitation Sobel algorithm is designed using structural Verilog lipoprotein synthesized exploitation Cadence Genus and enforced using Cadence Innovus. The practicality of the planning is verified exploitation normal pictures by FPGA implementation. The proposed architecture reduce the power, delay and space complexity compare to three existing architectures.