Transaction-based SoC design techniques for AMBA AXI4 bus interconnects using VHDL

• Published in: 2014 11th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) pp. 1 - 6
• Main Authors: Kho, Daniel C. K., Munusamy, Kumar
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2014
• Subjects: Clocks; Hardware; Physical layer; Ports (Computers); Protocols; Software; System-on-chip
• DOI: 10.1109/ECTICon.2014.6839715

Transaction-level Modeling (TLM) and bus functional modeling (BFM) are widely-used techniques for functional verification of digital systems. Many modern systems-on-chip (SoC), network-on-chip (NoC), application-specific integrated circuit (ASIC), and field-programmable gate array (FPGA) designs have been verified using these techniques. However, transaction-based techniques have almost always [1]-[14] been used only for simulation of digital designs, and until recently, were not used to design physical hardware. This paper introduces a technique to develop transaction-based hardware. With this method, the same transaction-based model can both be simulated and synthesized to hardware. Several SoC/NoC subsystems can easily be interconnected in basically the same manner as how transaction-based simulation models are being written. This approach brings the benefits of transaction-based verification (TBV) to the hardware design engineers, resulting in a greater level of simplification for complex designs.