Real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator for a multi-media SoC

• Published in: Proceedings of 2010 International Symposium on VLSI Design, Automation and Test pp. 21 - 24
• Main Authors: Higuchi, R, Teraoka, E, Higashida, M
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2010
• Subjects: Consumer products; Delay; Digital TV; Frequency conversion; Multimedia communication; Multimedia systems; Real time systems; SDRAM; Terminology
• ISBN: 9781424452699; 1424452694
• DOI: 10.1109/VDAT.2010.5496682

Latest multi-media SoCs used in a digital product such as digital TV have a structure where a number of IPs with real-time requirement share one channel of off-chip SDRAM using high-frequency bus to achieve multi-function, high-performance, and low-cost. Thus, such a bus system is required that satisfies real-time requirement, realizes high-efficiency, and has hierarchical structure. In this bus system, bus arbitration plays a crucial role. In this paper, we show Static arbitration has an advantage in bus efficiency over existing arbitration algorithms. And we propose a real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator and the Priority Level Transmission Mechanism. Simulation results show that the proposed bus system can satisfy real-time requirement, and is practical and efficient.