The defects analysis in CMOS fabrication by arrhenius activation energy technique

• Published in: 2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems pp. 437 - 440
• Main Authors: Pengchan, W., Phetchakul, T., Poyai, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2011
• Subjects: activation energy; Capacitance; Capacitance-voltage characteristics; CMOS; Current density; defect; fabrication; generation current; Leakage current; P-n junctions; Substrates
• ISBN: 1612847757; 9781612847757
• DOI: 10.1109/NEMS.2011.6017386

Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p + -n-well more than in n + -p-substrate. Finally, the possible nature of the defect will be discussed.