A 43-GHZ static frequency divider in 0.13μM standard CMOS

• Published in: 2008 Canadian Conference on Electrical and Computer Engineering pp. 000111 - 000114
• Main Authors: Bangli Liang, Dianyong Chen, Bo Wang, Dezhong Cheng, Kwasniewski, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2008
• Subjects: CML; CMOS logic circuits; Frequency conversion; frequency divider; Inductors; Optical buffering; Optical design; Optical fiber communication; Optical frequency conversion; Robustness; Shunt (electrical); Strontium
• ISBN: 9781424416424; 1424416426
• ISSN: 0840-7789; 2576-7046
• DOI: 10.1109/CCECE.2008.4564505

In this paper, a low supply static 2:1 frequency divider based on 0.13 mum CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The frequency divider uses a single 1.2-V supply voltage and consumes a total current of 32 mA. And the chip area is only 0.63 mm 2 with bonding pads.