A 30fJ/comparison dynamic bias comparator

A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed d...

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Bibliographic Details

Published in:	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference pp. 71 - 74
Main Authors:	Bindra, Harijot Singh, Lokin, Chris E., Annema, Anne-Johan, Nauta, Bram
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-09-2017
Subjects:	charge steering Delays double-tail latch-type comparator Dynamic bias Energy consumption Latches Noise Noise measurement Offset SAR Signal to noise ratio StrongARM latch Transistors Voltage measurement
Online Access:	Get full text
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