Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

• Published in: 2006 IEEE International Test Conference pp. 1 - 7
• Main Authors: Hyunbean Yi, Jaehoon Song, Sungju Park
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2006
• Subjects: Circuit faults; Circuit testing; Clocks; Delay; Fault detection; Integrated circuit interconnections; Logic; Semiconductor device modeling; System testing; Wires
• ISBN: 9781424402915; 1424402913
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2006.297632

This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments