Challenges for ultra-shallow junction formation technologies beyond the 90 nm node

• Published in: 11th IEEE International Conference on Advanced Thermal Processing of Semiconductors. RTP 2003 pp. 17 - 33
• Main Authors: Timans, P.J., Lerch, W., Niess, J., Paul, S., Acharya, N., Nenyei, Z.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Contact resistance; Ion implantation; Manufacturing; MOS devices; Optimization methods; Rapid thermal annealing; Shape; Temperature control; Thermal resistance; Thermal stresses
• ISBN: 0780378741; 9780780378742
• DOI: 10.1109/RTP.2003.1249120

The continuing scaling of MOS devices poses increasing challenges for the formation of ultra-shallow junctions (USJ). At the 90 nm device node USJ requirements for PMOS devices include junction depth below 25 nm and sheet resistance below 660 /spl Omega//square. Success in volume manufacturing also requires excellent repeatability and wafer uniformity, including optimization with respect to wafer pattern effects. This paper shows that sophisticated spike-annealing techniques combined with low-energy ion implantation can meet these requirements. For the 65 nm node, current methods will have to be augmented with optimized preamorphization and co-implantation techniques. The paper also examines the potential of new techniques such as millisecond annealing and solid-phase epitaxy (SPE). For millisecond annealing one of the major challenges arises from greatly magnified pattern effects combined with the very large thermal stresses induced by the enormous temperature gradients imposed on the wafer. SPE can provide the very shallow, highly activated junctions needed for advanced technologies but the issues of process integration and residual damage will require further development.