An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing

• Published in: 2011 IEEE 19th Annual International Symposium on Modelling, Analysis, and Simulation of Computer and Telecommunication Systems pp. 150 - 158
• Main Authors: Taecheol Oh, Kiyeon Lee, Sangyeun Cho
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2011
• Subjects: Analytical models; Bandwidth; Chip multiprocessor (CMP); Delay; Equations; Hidden Markov models; Mathematical model; performance modeling; Resource management; resource sharing; simulation
• ISBN: 9781457704680; 1457704684
• ISSN: 1526-7539; 2375-0227
• DOI: 10.1109/MASCOTS.2011.17

Processor cores in a chip multiprocessor (CMP) typically share a large last-level cache and the off-chip memory bandwidth. Previous studies demonstrate that explicit cache capacity and off-chip bandwidth partitioning can yield better overall system performance than without partitioning. However, little work has been done to study the interaction between cache capacity partitioning and off-chip bandwidth allocation. This paper develops a hybrid analytical model that takes into account the two partitioning problems together in order to capture their inter-dependence. With an elaborate case study, we show that an optimal resource management strategy would require a coordinated allocation of the cache and the off-chip bandwidth resources.