Design, analysis and performance comparison of GNRFET based 8-bit ALUs

• Published in: 2016 International Conference on Research Advances in Integrated Navigation Systems (RAINS) pp. 1 - 6
• Main Authors: Aradhya, H.V. Ravish, Madan, H.R., Suraj, M.S., Mahadikar, Megaraj T, Muniraj, R, Moiz, Mohammed, Bharadwaj, Abhijith A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2016
• Subjects: Adders; ALU; CMOS; Delays; Full adder; GNRFET; Graphene; Logic gates; Power demand; Power dissipation; Transistors
• DOI: 10.1109/RAINS.2016.7764366

The advancement in IC technology is primarily attributed to the MOSFET scaling theory. As the transistor size reduced, power consumption also reduced. As the process technology reached nano-meter regime, silicon CMOS started developing Short Channel Effects which led to increased power dissipation. A trade-off arose between power-dissipation and area. Alternatives to CMOS were found to avoid the trade-off. Graphene based transistor proved to be a potential replacement to CMOS. The Arithmetic and Logic Unit is the basic computing unit of all microprocessors or microcontrollers. The parallel adder forms the critical path in the ALU. The proposed work designs and compares CMOS and GNRFET based 8-bit ALU architectures. The first architecture contains 28TFA (Transistor Full Adder) and NAND based MUX design, second architecture-10TFA and NAND based MUX while third architecture-10TFA and TG (Transmission Gate) based MUX. The power dissipation and delay for three ALU architectures using GNRFET and CMOS respectively are 28TFA-ALU (0.1249pW, 24.58ps), (14.65pW, 47.908ps)), 10TFA-ALU ((0.1152pW, 18.117ps), (11.82pW, 42.964)) and TGMUX-ALU ((0.123pW, 15.799ps), (12.08pW, 37.542ps)). GNRFET based ALU shows 56%improvement in the PDPwhen compared to the CMOS based ALU.