High-level design error diagnosis using backtrace on decision diagrams

• Published in: NORCHIP 2010 pp. 1 - 4
• Main Authors: Raik, J, Repinski, U, Ubar, R, Jenihhin, M, Chepurov, A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-11-2010
• Subjects: Algorithm design and analysis; Benchmark testing; Circuit faults; Clocks; Design methodology; Hardware; Labeling
• ISBN: 1424489725; 9781424489725
• DOI: 10.1109/NORCHIP.2010.5669486

The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact all the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm.