Technology Adaptation in Logic Synthesis

• Published in: 23rd ACM/IEEE Design Automation Conference pp. 94 - 100
• Main Authors: Joyner, W.H., Trevillyan, L.H., Brand, D., Nix, T.A., Gundersen, S.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1986
• Subjects: Area measurement; Boolean functions; Decoding; Equations; Logic arrays; Logic design; Production systems; Testing; Timing; Transistors
• ISBN: 0818607025; 9780818607028
• ISSN: 0738-100X
• DOI: 10.1109/DAC.1986.1586074

Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to procedures attempting to satisfy a wider range of criteria. Gate or cell count, taken as a measure of area, continues to be a major factor in design acceptability, but timing constraints, testability, wirability, and efficient use of available primitives are important as well. Additional information, such as "don't care" conditions, can be used to improve the design quality. This paper describes how these requirements are specified to and enforced by the Logic Synthesis System (LSS), a tool which has been used in production on gate array chips. Trade-offs between varying requirements, and their effect on the logic produced, are discussed and illustrated with a standard set of examples.