Addressing key challenges in 1T-DRAM: Retention time, scaling and variability - Using a novel design with GaP source-drain

• Published in: 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) pp. 376 - 379
• Main Authors: Pal, Ashish, Nainani, Aneesh, Saraswat, Krishna C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2013
• Subjects: Gallium; Logic gates; Performance evaluation; Random access memory; Scalability; Silicon; Transistors
• ISBN: 9781467357333; 1467357332
• ISSN: 1946-1569; 1946-1577
• DOI: 10.1109/SISPAD.2013.6650653

We propose a vertical gate all around 1-transistor DRAM cell with silicon channel and gallium phosphide source drain (GaP-SD) as a viable alternative to the present 1T-1C DRAM technology. The valence band offset at GaP and Si interface helps to store more holes in the transistor body and thus improves the retention time by 2 order over conventional Si-SD 1T DRAM. By examining body thickness variability, we conclude that GaP-SD memory cell can withstand the performance degradation due to device variability to meet the ITRS retention time requirements. Finally the GaP-SD memory cell is optimized for scaled dimensions upto 20nm body thickness to establish its superiority at lower technology nodes.