Cyclic redundancy encoder for error detection in communication channels

• Published in: 2004 RF and Microwave Conference (IEEE Cat. No.04EX924) pp. 224 - 226
• Main Authors: Khalifa, O.O., Rafiqul Islam, M.D., Khan, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Arithmetic; Communication channels; Computer errors; Cyclic redundancy check; Digital communication; Error correction; Polynomials; Power engineering and energy; Power engineering computing; Transmitters
• ISBN: 9780780386716; 078038671X
• DOI: 10.1109/RFM.2004.1411112

This paper describes the methodology used and the implementation of the cyclic redundancy check (CRC) algorithm using C++ programming. The technique gained its popularity because it combines three advantages: extreme error detection capabilities, little overhead, and ease of implementation. The CRC is calculated by performing a modulo 2 division of the data by a generator polynomial and recording the remainder after division. The most commonly used polynomials are implemented. The conclusions and analysis results were shown and suggest that the cyclic redundancy check encoder be used in error detection for digital signals due to its ability to quickly determine if errors are present. The redundancy bits produced by the cyclic encoder enable the receiver to quickly determine if an error was produced. Different types of polynomials are used in the CRC.