Analysis of on-Line Computation Effectiveness in Redundant Number System

• Published in: 2018 IEEE First International Conference on System Analysis & Intelligent Computing (SAIC) pp. 1 - 6
• Main Authors: Dychka, Ivan, Zhabin, Valerii, Zhabina, Valentina
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2018
• Subjects: Copper; CSoC; Data communication; Data processing; Delays; Field programmable gate arrays; fine-grain algorithm; FPGA; Hardware; on-line computation; operation overlap; redundant number system; Signal processing algorithms
• DOI: 10.1109/SAIC.2018.8516877

There is investigated a possibility to increase the effectiveness of computation in systems on chip due to related operations overlap and necessary hardware resource reduction. Computing systems, where computation units are directly connected in accordance with a data flow graph, are considered. The graph nodes correspond to operations, and the arcs correspond to data. Direct data transmission between the units enables to decrease the time spent for complicated procedures of the data interchange with the use of the common address space. It is especially important for fine-grain algorithms realization. There is proposed an algorithm and respective structure of a computation unit that enables to execute two-, three- and four-place operations in on-line mode by means of digit by digit processing of data represented in redundant symmetrical number system. It is shown that the use of computation units that process operands digit by digit enables to execute sequences of operations connected by means of data in the concurrent mode at the level of operand digit processing. In comparison with the use of parallel units, the number of required internal commutation circuits and chip pinouts is reduced due to serial data transmission. Nevertheless, data processing speed is still high. There are given examples of scheme design for calculation of polynomials and many-input rational functions.